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參數(shù)資料
| 型號(hào)： | MB81V4265S-70L |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| 中文描述： | 的CMOS 256K × 16位的超頁模式動(dòng)態(tài)RAM的CMOS（256K × 16位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 653K |
| 代理商： | MB81V4265S-70L |
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DS05-10191-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
256 K
HYPER PAGE MODE DYNAMIC RAM
MB81V4265S-60/-70/-60L/-70L
×
16 BITS
CMOS 262,144
×
16 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V4265S is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory
cells accessible in 16-bit increments. The MB81V4265S features the “hyper page” mode of operation which
provides extended valid time for data output and higher speed random access of up to 512
the same row than the fast page mode. The MB81V4265S-60/-70/-60L/-70L DRAMs are ideally suited for memory
applications such as embedded control, buffer, portable computers, and video imaging equipment where very
low power dissipation and high bandwidth are basic requirements of the design.
The MB81V4265S is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft
errors and extends the time interval between memory refreshes.
×
16-bits of data within
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PRODUCT LINE & FEATURES
Parameter
MB81V4265S
-60L
-60
-70
-70L
RAS Access Time
CAS Access Time
Address Access Time
Random Cycle Time
Hyper Page Mode Cycle Time
60 ns max.
20 ns max.
30 ns max.
104 ns min.
25 ns min.
378 mW max.
7.2 mW
3.6 mW
70 ns max.
20 ns max.
35 ns max.
119 ns min.
30 ns min.
335 mW max.
7.2 mW
3.6 mW
Low Power
Dissipation
Operating Current
Standby
Current
LVTTL Level
CMOS Level
3.6 mW
540
3.6 mW
540
μ
W
μ
W
262,144 words
×
16 bits organization
Silicon gate, CMOS, Advanced Stacked
Capacitor Cell
All input and output are LVTTL compatible
512 refresh cycles every 8.2 ms
9 rows
×
9 columns, addressing scheme
Self refresh function
Standard and low power versions
Early Write or OE controlled Write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper page mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB81V4265S-70 | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| MB81V4400C-60 | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動(dòng)態(tài)RAM) |
| MB81V4400C-70 | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動(dòng)態(tài)RAM) |
| MB81V4405C-60 | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| MB81V4405C-70 | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
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