參數(shù)資料
型號(hào): MB81V4265-70
廠商: Fujitsu Limited
英文描述: CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 256K × 16位的CMOS超頁(yè)模式動(dòng)態(tài)RAM的CMOS(256K × 16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 18/27頁(yè)
文件大小: 366K
代理商: MB81V4265-70
18
MB81V4265-60/-70
LCAS
or
UCAS
Fig. 12 – HYPER PAGE MODE EARLY WRITE CYCLE
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
A
0
to A
8
WE
DQ
(Input)
V
OH
V
OL
DQ
(Output)
“H” or “L”
ROW
ADD
HIGH-Z
DESCRIPTION
The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of
WE and OE are reversed. Data appearing on the DQ1 to DQ8 is latched on the falling edge of LCAS and one appearing on the
DQ
9
to DQ
16
is latched on the falling edge of UCAS and the data is written into the memory. During the hyper page mode early
write cycle, including the delayed (OE) write and read-modify-write cycles, t
CWL
must be satisfied.
t
RASP
t
RP
t
RSH
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
CAS
t
HPC
t
CSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CAH
t
RAL
t
ASC
t
CAH
t
ASC
t
ASC
t
CAH
t
AR
t
RAH
t
ASR
t
WCR
t
WCS
t
CWL
t
WCH
t
WCS
t
CWL
t
WCH
t
WCH
t
WCS
t
CWL
t
RWL
t
DH
t
DS
t
DH
t
DS
t
DS
t
DH
t
DHR
COL
ADD
COL
ADD
COL
ADD
VALID
DATA
VALID
DATA
VALID
DATA
t
RHCP
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PDF描述
MB81V4265S-60 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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MB81V4265S-70L CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-70 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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