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參數(shù)資料
| 型號： | MB81V4265-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 256K ×16BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 256K × 16位的CMOS超頁模式動態(tài)RAM的CMOS（256K × 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 366K |
| 代理商： | MB81V4265-70 |
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MB81V4265-60/-70
LCAS
or
UCAS
LCAS
or
UCAS
Fig. 16 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
A
0
to A
8
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
RAS
DQ
(Output)
ROW ADDRESS
“H” or “L”
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row
addresses every 8.2-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be re-
freshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
“H” or “L”
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS
is held Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh ad-
dress counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incre-
mented in preparation for the next CAS-before-RAS refresh operation.
DQ
(Output)
HIGH-Z
t
RAS
t
RC
t
RP
t
RPC
t
CRP
t
RAH
t
ASR
t
CRP
t
OFF
t
OH
HIGH-Z
t
RC
t
RP
t
RAS
t
CPN
t
CSR
t
CHR
t
RPC
t
CSR
t
CPN
t
OFF
t
OH
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| MB81V4265S-60 | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級頁面存取模式動態(tài)RAM) |
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| MB81V4265S-70 | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級頁面存取模式動態(tài)RAM) |
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