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| 型號： | MB81V4405C-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 348K |
| 代理商： | MB81V4405C-60 |
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MB81V4405C-60/MB81V4405C-70
CAS
Fig. 21 – SELF REFRESH CYCLE (A
0
- A
9
= OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
Parameter
Unit
Min.
Max.
No.
Min.
Max.
100
—
100
100
Symbol
101
119
—
—
104
102
–50
–50
—
—
—
μ
s
ns
ns
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB81V4405C-60
MB81V4405C-70
t
RASS
t
RPS
t
CHS
“H” or “L”
V
IH
V
IL
RAS
V
IH
V
IL
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is
operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s),
the device can be entered the self refresh cycle. And after that, refresh operation is automatically executed per fixed interval using internal
refresh address counter during “RAS = L” and “CAS = L”.
And exit from self refresh cycle is performed by toggling of RAS and CAS to “H” with specifying t
CHS
min..
Restruction for Self refresh operation;
For self refresh operation, the notice below must be considered.
1) In the case that distribute CBR refresh are operated in read/write cycles
Self refresh cycles can be executed without special rule if 1024 cycles of distribute CBR refresh are executed within t
REF
max..
2) In the case that burst CBR refresh or RAS only refresh are operated in read/write cycles
1024 times of burst CBR refresh or 1024 times of burst RAS only refresh must be executed before and after Self refresh
cycles.
1024 times of burst refresh
1024 times of burst refresh
Read/Write operation
Self Refresh operation
t
RASS
Read/Write operation
V
IH
V
IL
RAS
t
NS
< 1 ms
t
SN
< 1 ms
HIGH-Z
V
IH
V
IL
V
OH
V
OL
WE
DQ
(Output)
t
RASS
t
RPS
t
RPC
t
CHS
t
CSR
t
CPN
t
OFF
t
OH
t
WHR
t
WSR
Note: Assumes self refresh cycle only
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