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參數(shù)資料
| 型號： | MB81V4800S-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 8位快速頁面模式的DRAM（的CMOS為512k × 8位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 19/26頁 |
| 文件大小： | 328K |
| 代理商： | MB81V4800S-70 |
19
MB81V4800S-60/MB81V4800S-70
Fig. 13 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1024 row
addresses every 16.4-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched
on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
“H” or
HIGH-Z
ROW ADDRESS
V
IH
V
IL
CAS
RAS
V
IH
V
IL
V
IH
V
IL
A
0
to A
9
DQ
(Output)
V
OH
V
OL
t
RC
t
RP
t
ASR
t
RPC
t
RAH
t
OH
t
RAS
t
OFF
t
CRP
HIGH-Z
t
CPN
t
CSR
t
CHR
t
RPC
Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
CAS
V
OH
V
OL
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held
Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address
counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented
in preparation for the next CAS-before-RAS refresh operation.
“H” or
t
RC
t
RAS
t
RP
t
OFF
t
OH
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