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| 型號(hào)： | MB81V4800S-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁(yè)面存取模式動(dòng)態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 8位快速頁(yè)面模式的DRAM（的CMOS為512k × 8位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 9/26頁(yè) |
| 文件大?。?/td> | 328K |
| 代理商： | MB81V4800S-70 |
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9
MB81V4800S-60/MB81V4800S-70
Notes: 1.
Referenced to V
SS
. To all V
CC
(V
SS
) pins, the same supply voltage should be applied.
I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open.
I
CC
depends on the number of address change as RAS = V
IL
and CAS = V
IH
, V
IL
> –0.5 V.
I
CC1
, I
CC3
and I
CC5
are specified at one time of address change during RAS = V
IL
and CAS = V
IH
.
I
CC4
is specified at one time of address change during one Page cycle.
An Initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-
only cycles before proper device operation is achieved. In case of using internal refresh counter, a
minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
AC characteristics assume t
T
= 5 ns.
Input voltage levels are 0 V and 3.0 V, and input reference levels are V
IH
(min.) and V
IL
(max.) for
measuring timing of input signals. Also, the transition time (t
T
) is measured between V
IH
(min.) and V
IL
(max.).
The output reference levels are V
OH
= 2.0 V and V
OL
= 0.8 V.
Assumes that t
RCD
≤
t
RCD
(max.), t
RAD
≤
t
RAD
(max.). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown. Refer
to Fig. 2 and 3.
If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
Measured with a load equivalent to one TTL loads and 100 pF.
10. t
OFF
and t
OEZ
is specified that output buffer change to high impedance state.
11. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. t
RCD
(min.) = t
RAH
(min.) + 2t
T
+ t
ASC
(min.).
13. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as
a reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
15. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min.) the data output pin will remain High-Z
state through entire cycle.
16. Assumes that t
WCS
< t
WCS
(min.).
17. Either t
DZC
or t
DZO
must be satisfied.
18. t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max.).
19. Assumes that CAS-before-RAS refresh.
2.
3.
4.
5.
6.
7.
8.
9.
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