
FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
MB86293 CORAL_LQ
Graphics Controller
Specifications Rev. 1.1
155
HTP (Horizontal Total Pixels)
Register
address
Bit number
Bit field name
R/W
Initial value
DisplayBaseAddress + 06
H
15
14
Reserved
R0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HTP
RW
Don’t care
This register controls the horizontal total pixel count. Setting value + 1 is the total pixel count.
HDP (Horizontal Display Period)
Register
address
Bit number
Bit field name
R/W
Initial value
DisplayBaseAddress + 08
H
15
14
Reserved
R0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HDP
RW
Don’t care
This register controls the total horizontal display period in unit of pixel clocks. Setting value + 1 is the
pixel count for the display period.
HDB (Horizontal Display Boundary)
Register
address
Bit number
Bit field name
R/W
Initial value
DisplayBaseAddress + 0A
H
15
14
Reserved
R0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HDB
RW
Don’t care
This register controls the display period of the left part of the window in unit of pixel clocks. Setting
value + 1 is the pixel count for the display period of the left part of the window. When the window is
not divided into right and left before display, set the same value as HDP.
HSP (Horizontal Synchronize pulse Position)
Register
address
Bit number
15
Bit field name
R/W
Initial value
DisplayBaseAddress + 0C
H
14
Reserved
R0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HSP
RW
Don’t care
This register controls the pulse position of the horizontal synchronization signal in unit of pixel clocks.
When the clock count since the start of the display period reaches setting value + 1, the horizontal
synchronization signal is asserted.
HSW (Horizontal Synchronize pulse Width)
Register
address
Bit number
Bit field name
R/W
Initial value
DisplayBaseAddress + 0E
H
7
6
5
4
3
2
1
0
HSW
RW
Don’t care
This register controls the pulse width of the horizontal synchronization signal in unit of pixel clocks.
Setting value + 1 is the pulse width clock count.