
FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
MB86293 CORAL_LQ
Graphics Controller
Specifications Rev. 1.1
169
L3OA0 (L3 layer Origin Address 0)
Register
address
Bit number
31 3029 28 2726 25 24 23 2221 20 1918 17 1615 1413 12 1110 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
R0
Initial value
0
DisplayBaseAddress + 5C
H
L3OA0
RW
R0
0000
Don’t care
This register sets the origin address of the logic frame of the L3 layer in frame 0. Since lower 4 bits
are fixed to “0”, this address is 16-byte aligned.
L3DA0 (L3 layer Display Address 0)
Register
address
Bit number
31 3029 28 2726 25 24 23 2221 20 1918 17 1615 1413 12 1110 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
R0
Initial value
0
DisplayBaseAddress + 60
H
L3DA0
RW
Don’t care
This register sets the origin address of the L3 layer in frame 0. For the direct color mode (16
bits/pixel), the lower 1 bit is “0” and this address is 2-byte aligned.
L3OA1 (L3 layer Origin Address 1)
Register
address
Bit number
31 3029 28 2726 25 24 23 2221 20 1918 17 1615 1413 12 1110 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
R0
Initial value
0
DisplayBaseAddress + 64
H
L3OA1
RW
R0
0000
Don’t care
This register sets the origin address of the logic frame of the L3 layer in frame 1. Since lower 4-bits
are fixed to “0”, this address is 16-byte aligned.
L3OA1 (L3 layer Display Address 1)
Register
address
Bit number
31 3029 28 2726 25 24 23 2221 20 1918 17 1615 1413 12 1110 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
R0
Initial value
0
DisplayBaseAddress + 68
H
L3DA1
RW
Don’t care
This register sets the origin address of the L3 layer in frame 1. For the direct color mode (16
bits/pixel), the lower 1 bit is “0” and this address is 2-byte aligned.
L3DX (L3 layer Display position X)
Register
address
Bit number
Bit field name
R/W
Initial value
DisplayBaseAddress + 6C
H
15
14
Reserved
R0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
L3DX
RW
Don’t care
This register sets the display starting position (X coordinates) of the L3 layer on the basis of the origin
of the logic frame in pixels.