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參數(shù)資料
| 型號(hào)： | MB86836PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit Embedded Controller |
| 中文描述： | 32-BIT, 90 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 12 X 12 MM, PLASTIC, FBGA-144 |
| 文件頁數(shù)： | 48/82頁 |
| 文件大?。?/td> | 1373K |
| 代理商： | MB86836PBT |
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MB86830 Series
48
(Continued)
(V
DD3
=
3.3 V
±
0.15 V, V
SS
=
0.0 V, T
A
=
0
°
C to
+
70
°
C)
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (V
SS
=
0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
Do not leave more than one output pins short-circuited for 1 second or more.
The external output load capacitance is 30 pF.
The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
These specifications are subject to change for improvement.
The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40 MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100
μ
s later.
An AC characteristic of pins and internal maximum operation frequency is separately defined.
The maximum operation frequency of an external bus is 40MHz though the maximum internal operation
frequency are 80 MHz or 100 MHz (CLKIN Min.=25ns).Therefore,when an external bus is used with 40MHz,
an internal frequency are 84 MHz and 100 MHz.
Relation between external bus clock and internal clock
Classifica-
tion
Parameter
Symbol
Value
MB86835
Min.
2
2
2
2
Asynchronous
Asynchronous
2
×
P
+
10
2
×
P
+
10
Unit
Max.
15
15
15
15
DRAMC
output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
“H” level period
“L” level period
RAS0# to RAS3#
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
IRC nput
IRQ15 to IRQ8
CLKIN
MB86835(84MHz)
×
3
60 MHz
×
1
×
2
×
4
×
5
N/A
20 MHz
20 MHz
40 MHz
80 MHz
33.3 MHz
33.3 MHz
66.6 MHz
N/A
N/A
N/A
40 MHz
40 MHz
80 MHz
N/A
N/A
N/A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86836PMT2 | 32-bit Embedded Controller |
| MB86941PFV | Peripheral LSI for SPARClite |
| MB86941 | Peripheral LSI for SPARClite |
| MB86942 | Peripheral LSI for SPARClite |
| MB86942PFV | Peripheral LSI for SPARClite |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86836PMT2 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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