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參數(shù)資料
| 型號： | MB86942PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Peripheral LSI for SPARClite |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 12/49頁 |
| 文件大?。?/td> | 598K |
| 代理商： | MB86942PFV |
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12
MB86941/942
(Continued)
Pin symbol
I/O
Pin no.
Pin name
Description
TCLK0#
I
41
Transmit Clock 0
Transmit Clock input pin
In synchronous mode, the sending bit rate is fixed at
the sending clock
×
1, so that the clock signal input at
these pins becomes the sending bit rate.
In asynchronous mode, the sending bit rate will be the
sending clock signal
×
1, or
×
1/16, or
×
1/64 depending
on the bit rate setting in the mode register.
For example, if a 19.2 kHz clock signal is input at the
TCLK# pin, the sending bit rate will be 19200 pbs with
an
×
1 setting, or 1200 pbs with an
×
1/16 setting, or
300 pbs with an
×
1/64 setting.
Sending data is output in synchronization with the
falling edge of the sending clock signal.
TCLK1#
I
48
Transmit Clock 1
RCVDT0
I
40
Receive Data 0
Receive Data input pin
Serial data input to these pins is converted to parallel
data in the SDTR module and then can be read by the
data bus.
RCVDT1
I
50
Receive Data 1
RCLK0
I
34
Receive Clock 0
Receive Clock input pin
In synchronous mode, the receiving bit rate is fixed at
the receiving clock
×
1, so that the clock signal input at
these pins becomes the receiving bit rate.
In asynchronous mode, the receiving bit rate will be
the sending clock signal
×
1, or
×
1/16, or
×
1/64
depending on the bit rate setting in the mode register.
For example, if a 19.2 kHz clock signal is input at the
RCLK pin, the receiving bit rate will be 19200 pbs with
an
×
1 setting, or 1200 pbs with an
×
1/16 setting, or
300pbs with an
×
1/64 setting.
Receiving data is sampled in synchronization with the
rising edge of the receiving clock signal.
Note that in asynchronous mode
×
1 speed differs from
×
1/16 and
×
1/64 speeds in that external
synchronization of the RCLK and RCVDT signals is
required.
RCLK1
I
51
Receive Clock 1
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| MB86960 | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
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| MB86950BPD-G | 制造商:FUJITSU 功能描述: |
| MB86960 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86960APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APD-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
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