- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377895 > MB86967PFV (FUJITSU LTD) LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces PDF資料下載
參數(shù)資料
| 型號(hào)： | MB86967PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| 中文描述： | 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 20/129頁(yè) |
| 文件大小： | 1499K |
| 代理商： | MB86967PFV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)
20
MB86967
5. Buffer Access
The Buffer Memory Port register pair BMPR8 and BMPR9 provide 8- or 16-bit data access to the receive and
transmit buffers through on-chip FIFOs. To eliminate the need for complicated directional control, FIFOs are
dedicated to each direction of data transfer. Writing to the transmit buffer can be interleaved with reading from
the receive buffer, with the MB86967 automatically maintaining buffer memory pointers, thus relieving the host
of that task. The Buffer Memory port register pair is at address 08H when DLCR7<3:2> are programmed to ‘10’
to select the Buffer Memory Port register set. When using DMA, the buffer memory port is automatically selected
when the DMA Acknowledge input, DMACK, is asserted. The host accesses are byte-wide when the system is
configured for byte-wide operation and word-wide when the system interface is configured for word-wide
operation. In the latter mode, byte-wide access to the buffer memory port is not supported.
Data can transfer from the host memory to the transmit buffer, or from the receive buffer to host memory by
using string moves, single-transfer programmed I/O moves, or DMA. Select the method that yields the highest
system-level efficiency. A rapid transfer process results in best performance. Slow transfer can result in poor
throughput and performance, and cause the receive buffer to overflow and lose packets.
6. DMA Operation (ISA, Generic Mode Only)
The MB86967 supports single-cycle and burst DMA operation for data transfers between the host and the packet
buffer. Hand-shaking between the MB86967 and the external DMA controller is accomplished by the DREQ and
DMACK signals. The end of process input, when asserted by the system DMA controller during a transfer cycle,
terminates DMA activity after completion of the current cycle. If a DMA interrupt (DLCR3<5>) is enabled, the
MB86967 generates an interrupt after completion of DMA activity.
Usually only one DMA operation will be run at a time, although the MB86967 could run two interleaving
operations, one reading and one writing. There is only one DMA EOP bit, and only one DREQ pin and one
DMACK pin, so most hosts could not support more than one DMA operation at a time.
6.1 DMA Write (Transmit) ISA, Generic Mode Only
Setting the TX DMA Enable bit, BMPR12<0>, enables DMA transfer of data packets from the host memory to
the MB86967 transmit buffer. The DMA burst control bits, BMPR13<1:0>, set the maximum number of data
transfer cycles (bytes or words) in a single bus acquisition to be 1, 4, 8, or 12. The MB86967, when ready to
accept data from the host, sets the DMA request output, DREQ, and the host responds by asserting DMA
acknowledge, DMACK, followed by Write Strobe, WR, and placing data on the data bus. The MB86967 asserts
the RDY(RDY) output when ready to complete the current data-transfer cycle. (The assertive states of the
RDY(RDY) output and the EOP(EOP) input are independently programmable.) The MB86967 accepts the data
byte/word into its bus write FIFO and later moves it into buffer memory. At the close of a transfer cycle, the host
negates WR. In burst mode and depending on the value of the DREQ EXTND bit, DLCR4<2>, the MB86967
negates DREQ at the next-to-last or last transfer cycle of the burst. The host DMA then completes the last one
or two transfer cycles and negates DACK to terminate the burst. To start another burst, the MB86967 reasserts
DREQ.
The DMA controller asserts the end of process input, EOP(EOP), concurrent with the last required data-transfer
cycle to indicate completion of the entire transfer process. This action sets the DMA EOP status bit, DLCR1<5>,
and discontinues further data requests from the MB86967. The MB86967 will also generate an interrupt if the
DMA EOP interrupt enable bit, DLCR3<5>, is high. The host can use this interrupt to begin action to close the
process. The host should reset the MB86967 DMA logic and clear the interrupt by writing 00H to BMPR12.
Note: DMA EOP DLCR1<5> must be cleared to close the transmit DMA process before attempting another
DMA process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will
clear automatically, clearing the EOP status and interrupt, (if enabled) so it is not necessary to clear the
interrupt separately.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86977 | IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | IP PACKET FORWARDING ENGINE |
| MB86H20 | SmartMPEG |
| MB86H21 | MPEG-2 Decoder with Integrated NDS ICAM |
| MB86H22 | MPEG-2 Decoder for ext. Temperature Range |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。