- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377895 > MB86967PFV (FUJITSU LTD) LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces PDF資料下載
參數(shù)資料
| 型號： | MB86967PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| 中文描述： | 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 8/129頁 |
| 文件大?。?/td> | 1499K |
| 代理商： | MB86967PFV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁
8
MB86967
System interface pins in ISA bus mode
(Continued)
Pin no.
18 to 23,
25,
27 to 29,
85,
87 to 91
4 to 13
Symbol
SD0 to SD15
Pin name
I/O
BD
Function
SYSTEM DATA BUS
These pins are used as data buses for data
exchange between the host system and the
MB86967. They are also used for DMA transfer. In
the 8-bit bus mode (bit 5 of DLCR6 = 1), only the 8
lower bits (SD0 to SD7) are used.
These pins are used for input of system address
signals for selecting LAN controller registers.
ISU This pin is used for input of hardware reset signals.
SA0 to SA9
SYSTEM ADDRESS
BUS
CHIP RESET
(Active High)
I/O READ
(Active Low)
I/O WRITE
(Active Low)
ADDRESS ENABLE
(Active High)
END OF PROCESS
(Active High or Active
Low)
ID
64
CHRESET
15
IOR
IU
This pin is used for input of I/O read strobe signals.
17
IOW
IU
This pin is used for input of I/O write strobe signals.
63
AEN
ISD This pin is used for input of signals indicating that the
DMA controller controls the system bus.
ID
This pin is used for input of signals indicating the end
of DMA transfer between the buffer memory and host
system. At input of EOP the next BREQ is not output
and the handshaking cycle is terminated.
ID
This pin is used for input of signals indicating that the
addresses of SA0 to SA9 are determined.
IU
This pin is used for controlling byte/word transfer. In
the 16-bit data bus mode (bit 5 (SB/SW) of DLCR6 =
0), this pin, together with SA0, controls word transfer
and the transfer of upper and lower bytes on the data
bus.
65
EOP
14
ALE
ADDRESS LATCH
ENABLE
SYSTEM BUS HIGH
ENABLE
82
SBHE
×
: don’t care
This pin is used for output of DMA transfer request
signals.
2
DREQ
DMA REQUEST
(Active High)
O
SB/SW
0
SBHE
0
SA0
0
Function
Word transfer
Transfer of upper bytes on
data bus (SD15 to SD8)
Transfer of lower bytes on
data bus (SD7 to SD0)
Unused
Byte transfer
(SD7 to SD0)
0
0
1
0
1
0
0
1
1
1
×
×
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86977 | IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | IP PACKET FORWARDING ENGINE |
| MB86H20 | SmartMPEG |
| MB86H21 | MPEG-2 Decoder with Integrated NDS ICAM |
| MB86H22 | MPEG-2 Decoder for ext. Temperature Range |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。
