參數(shù)資料
型號(hào): MB86R01PB-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 39/89頁(yè)
文件大?。?/td> 0K
描述: IC SOC GRAPHIC CONTRLR 484BGA
特色產(chǎn)品: Graphics Display Controllers (GDC)
標(biāo)準(zhǔn)包裝: 40
系列:
應(yīng)用: 圖形控制器
核心處理器: ARM9
程序存儲(chǔ)器類(lèi)型: 外部程序存儲(chǔ)器
控制器系列:
RAM 容量: 64K x 8
接口: ADC,ATA,CAN,EBI/EMI,I²C,I²S,媒體 LB,PWM,SD 卡,UART/USART,USB
輸入/輸出數(shù): 24
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 484-BGA
包裝: 托盤(pán)
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
其它名稱(chēng): 865-1110
38
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
8.3.
Precautions at Power On
8.3.1.
Recommended Power On/Off Sequence
Follow the power on/off sequence as shown below:
<ON>: VDDI (internal and PLLVDD)
→ DDRVDE (external) → VDDE (external) → Signal
<OFF>: Signal
→ VDDE (external) → DDRVDE (external) → VDDI (internal and PLLVDD)
VDDI
VDDE
DDRVDE
Figure 8-1
Recommended Power On/Off Sequence (1)
There is no limitation on the sequence of power on/off of VDDI, VDDE, and DDRVDE if the following
condition is met. (Figure 8-2)
Do not apply VDDE and DDRVDE (external) continuously more than 1 second when VDDI (internal)
is off.
VDDE
1 sec. or less
VDDI
1 sec. or less
DDRVDE
Figure 8-2
Recommended Power On/Off Sequence (2)
Perform power on/off for VREF according to the DDR2-SDRAM regulation.
Perform power on/off so that power for PLLVDD (PLL) does not exceed VDDI.
Turn on all power. Turning on only a part of them is prohibited.
CMOS IC becomes unstable immediately after power-on so that proceed reset immediately.
Set the reset pins (XTRST and XRST) to Low when power-on.
Input clock to CLK pin immediately after power-on.
It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST pin to
be transmitted to all internal circuits.
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