參數(shù)資料
型號(hào)： MB86R01PB-GSE1
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 83/89頁(yè)
文件大?。?/td> 0K
描述： IC SOC GRAPHIC CONTRLR 484BGA
特色產(chǎn)品： Graphics Display Controllers (GDC)
標(biāo)準(zhǔn)包裝： 40
系列： 玉
應(yīng)用： 圖形控制器
核心處理器： ARM9
程序存儲(chǔ)器類(lèi)型： 外部程序存儲(chǔ)器
控制器系列： 玉
RAM 容量： 64K x 8
接口： ADC，ATA，CAN，EBI/EMI，I²C，I²S，媒體 LB，PWM，SD 卡，UART/USART，USB
輸入/輸出數(shù)： 24
電源電壓： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 484-BGA
包裝： 托盤(pán)
供應(yīng)商設(shè)備封裝： 484-BGA（23x23）
其它名稱(chēng)： 865-1110
78
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
8.5.14.2.
IDE Ultra DMA Timing
Table 8-51
AC timing of Ultra DMA
Value
mode0
mode1
mode2
mode3
mode4
Symbol
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
T2cycleTYP
Typical sustained average 2 cycle
time
240
–
160
–
120
–
90
–
60
–
ns
T2cycle
2 cycle time allowing for clock
variations (from rising edge to next
rising edge or from falling edge to
next falling edge of STROBE)
230
–
154
–
115
–
86
–
57
–
ns
Tcycle
Cycle time allowing for asymmetry
and clock variations (from STROBE
edge to STROBE edge)
112
–
73
–
54
–
39
–
25
–
ns
Tdvs
Data valid setup time at sender (from
data valid until STROBE edge)
70
–
48
–
30
–
20
–
6.7
–
ns
Tdvh
Data valid setup time at sender (from
STROBE edge until data may
become invalid)
6.2
–
6.2
–
6.2
–
6.2
–
6.2
–
ns
Tfs
First STROBE time (for device to
first negateDSTROBE from STOP
during data in Burst)
–
230
–
200
–
170
–
130
–
120
ns
Tli
Limited interlock time
0
150
0
150
0
150
0
100
0
100
ns
Tmli
Interlock time with minimum
20
–
20
–
20
–
20
–
20
–
ns
Tui
Unlimited interlock time
0
–
0
–
0
–
0
–
0
–
ns
Taz
Maximum time allowed for output
drivers to release (from asserted or
negated)
–
10
–
10
–
10
–
10
–
10
ns
Tzah
Minimum delay time required for
output
20
–
20
–
20
–
20
–
20
–
ns
Tzad
Drivers to assert or negate (from
released)
0
–
0
–
0
–
0
–
0
–
ns
Tenv
Envelope time (from DMACK- to
STOP and HDMARDY- during data
in burst initiation and from
IDE_XDDDMACK to STOP during
data out burst initiation)
20
70
20
70
20
70
20
55
20
55
ns
Trfs
Ready-to-final-STROBE time (no
STROBE edges shall be sent this
long after negation of DMARDY)
–
75
–
70
–
60
–
60
–
60
ns
Trp
Minimum time to assert STOP or
negate IDE_DMARQ
160
–
125
–
100
–
100
–
100
–
ns
Tiordyz
Maximum time before releasing
IDE_DIORDY
–
20
–
20
–
20
–
20
–
20
ns
tziordy
Minimum time before driving
STROBE
0
–
0
–
0
–
0
–
0
–
ns
Tack
Setup and hold times for DMACK-
(before assertion or negation)
20
–
20
–
20
–
20
–
20
–
ns
Tss
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates burst)
50
–
50
–
50
–
50
–
50
–
ns
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