參數(shù)資料
型號(hào)： MB86R01PB-GSE1
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 89/89頁(yè)
文件大?。?/td> 0K
描述： IC SOC GRAPHIC CONTRLR 484BGA
特色產(chǎn)品： Graphics Display Controllers (GDC)
標(biāo)準(zhǔn)包裝： 40
系列： 玉
應(yīng)用： 圖形控制器
核心處理器： ARM9
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
控制器系列： 玉
RAM 容量： 64K x 8
接口： ADC，ATA，CAN，EBI/EMI，I²C，I²S，媒體 LB，PWM，SD 卡，UART/USART，USB
輸入/輸出數(shù)： 24
電源電壓： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
包裝： 托盤
供應(yīng)商設(shè)備封裝： 484-BGA（23x23）
其它名稱： 865-1110
3
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
AHB1 bus
Following resources are connected.
CPU core: Bus masters of instruction (I)/data (D)
GDC: GDC register part
AHB2AXI: AXI port for main memory access
CCPB: Encrypted ROM decoding block
External BUS I/F: External bus interface (connected through CCPB)
SRAM: General purpose internal SRAM 32KB × 2
DMAC: General purpose DMA × 8ch
It operates as bus master at data transfer
Boot ROM: Built-in boot ROM
I2S_0/1/2: Serial audio controller × 3ch
USB 2.0 Function DMAC: USB function DMAC
It operates as bus master at data transfer
USB2.0 Host: It operates as USB2.0 EHCI, USB1.1 OHCI bus masters
IDE66/IDE66DMAC: Register part of IDE host controller and built-in DMAC
The DMAC part operates as bus master at data transfer
MLB: MediaLB controller
AHB2
APBBRG0/1/2: AHB-APB bridge circuit × 3ch
AHB2 bus
CCPB: Encrypted ROM decoding block
USB 2.0 Function: USB 2.0 function controller's register part
USB 2.0 Host: USB 2.0 host controller's register part
SDMC: SD memory controller
DDR2 controller: DDR2 controller's register part
APB_TOP_0
This block bridges between APBBRG0 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
Interrupt controller (IRC) × 2ch
External interrupt controller (EXTIRC)
Clock reset generator (CRG)
UART (ch0 and ch1) × 2ch
Remap boot controller (RBC)
32 bit general-purpose timer (32 bit timer) × 2ch
APB_TOP_1
This block bridges between APBBRG1 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
I2C controller × 2ch
CAN controller × 2ch
UART (ch2 and ch3) × 2ch
A/D converter (ADC) × 2ch
APB_TOP_2
This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
PWM controller (PWM)
SPI controller (SPI)
CCNT
UART (ch4 and ch5) × 2ch
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