參數(shù)資料
型號: MB89374
廠商: Fujitsu Limited
英文描述: Data Link Controller (DLC)(數(shù)據(jù)鏈接控制器)
中文描述: 數(shù)據(jù)鏈路控制器(金剛石)(數(shù)據(jù)鏈接控制器)
文件頁數(shù): 32/45頁
文件大?。?/td> 328K
代理商: MB89374
32
MB89374
(37) Transmit Clock and Transmit Data
(V
CC
= +5 V
±
10%, V
SS
= 0 V, Ta = 0
°
C to +70
°
C)
Min.
4t
CK
(Note 2)
1t
CK
+ 40
(Note 3)
1t
CK
+ 40
(Note 3)
Parameter
Symbol
t
STXRDYL
t
STXCW
t
STXCL
t
STXCH
t
STXDD
t
SLOCD
Max.
6t
CK
100
100
Unit
IRQ
delay (T
X
C#
) (Note 1)
T
X
CI# clock period
LOW-level T
X
CI# clock pulse duration
HIGH-level T
X
CI# clock pulse duration
T
X
D delay (T
X
C#)
LOC# delay (T
X
C#)
Notes: 1. TxC# denotes T
X
CI# or TxCO#; RxC# denotes RxCI# or RxCO#
2. In LOOP mode: if NRZ or NRZI code, the minimum level is 8 t
CK
; if FM0, FM1, or Manchester code,
the minimum level is 12 t
CK
.
3. In LOOP mode: if NRZ or NRZI code, the minimum level is 3 t
CK
+40; if FM0, FM1, or Manchester code,
the minimum level is 5 t
CK
+40.
ns
t
STXCW
t
STXCH
t
STXDD
IRQ
t
STXDD
t
SLOCD
t
STXRDYI
LOC#
T
X
D *2
T
X
CI#, T
X
C O#
*1
*1: No change if NRZ or NZRI code
*2: When the Send High (SH) or Send Break (SB) bit of the TxCR register is enabled, output is assumed after a
maximum of 3 t
CK
from the rising edge of WR# (DS#).
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