參數(shù)資料
型號(hào)： MB89374
廠商： Fujitsu Limited
英文描述： Data Link Controller (DLC)(數(shù)據(jù)鏈接控制器)
中文描述： 數(shù)據(jù)鏈路控制器（金剛石）（數(shù)據(jù)鏈接控制器）
文件頁(yè)數(shù)： 5/45頁(yè)
文件大?。?/td> 328K
代理商： MB89374
5
MB89374
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(Continued)
Pin No.
DIP
Symbol
I/O
Level*
Description
QFP
32
7
T
X
LAST#/CI#
I
—
Transmit DMA-end-signal or calling-indication pin:
This pin serves as the TxLAST# input pin when the DMA
mode is selected by the TxD/I bit of the transmit interrupt
enable register (TxIER), and by the enabling TxLASTEND
bit of the transmit mode register (SMR3). In other cases,
this pin serves as the CI# input pin. If this pin is used as the
CI# input pin, the CI bit of the modem status register (MSR)
displays 1 when the pin input level is LOW, and 0 when the
input level is HIGH.
Transmit-data pin:
This pin is used to output serial data.
Receive-data pin:
This pin is used to input serial data.
Source-clock input or data-set-ready pin:
This pin serves as the SCLK input pin for BRG1/BRG2 or
DPLL when:
BRG, DPLL or BRG + DPLL are selected by the TxC0 and
TxC1 bits of the transfer mode register (SMR2).
BRG, DPLL or BRG + DPLL are selected by the RxC0 and
RxC1 bits of the transfer mode register (SMR2).
The BRG1OUTIE bit of the BRG1/DPLL control register
(B1PCR) is set to 1.
The BRG2CLK bit of the BRG2 control register (B2CR) is
set to 1.
In other cases, this pin serves as the DSR# input pin.
If this pin is used as the DSR# input pin, the DSR bit of the
modem status register (MSR) displays 1 when the pin input
level is LOW, and 0 when the input level is HIGH.
BRG2 clock-input pin:
This pin is used only when the clock source for BRG2 is not
set at the SCLK pin (by setting the BRG2CLK bit of the
BRG2 control register (B2CR)).
Reset pin:
This pin is used to input system reset signals.
Read/data strobe pin:
This pin serves as the RD# input pin in the MBL8086/88
mode. A LOW level is input to this pin when reading the
registers in the DLC.
This pin serves as the DS# input pin in the GMICRO mode.
Strobe signals are input to this pin when accessing the
registers in the DLC.
29
4
T
X
D
O
H
28
3
R
X
D
I
—
33
8
SCLK/DSR#
I
—
23
45
TCLK
I
—
3
22
RESET#
I
—
4
23
RD#/DS#3
I
—
Signals suffixed by the symbol # are negative logic.
* :Pin output level when reset
相關(guān)PDF資料
PDF描述
MB89470 8-bit Proprietary Microcontroller
MB89475 8-bit Proprietary Microcontroller
MB89475PFM 8-bit Proprietary Microcontroller
MB89475PFV 8-bit Proprietary Microcontroller
MB89475P-SH 8-bit Proprietary Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB89470 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89475 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89475PFM 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89475PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89475P-SH 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
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