參數(shù)資料
型號(hào): MB89374
廠商: Fujitsu Limited
英文描述: Data Link Controller (DLC)(數(shù)據(jù)鏈接控制器)
中文描述: 數(shù)據(jù)鏈路控制器(金剛石)(數(shù)據(jù)鏈接控制器)
文件頁(yè)數(shù): 33/45頁(yè)
文件大小: 328K
代理商: MB89374
33
MB89374
(38) Receive Clock and Receive Data
(V
CC
= +5 V
±
10%, V
SS
= 0 V, Ta = 0
°
C to +70
°
C)
Min.
4t
CK
(Note 2)
1t
CK
+ 40
(Note 3)
1t
CK
+ 40
(Note 3)
0
160
Parameter
Symbol
t
SRXRDYI
t
SRXCW
t
SRXCL
t
SRXCH
t
SRXDS
t
SRXDH
t
FD
Max.
4t
CK
3t
CK
Unit
IRQ
delay (R
X
C#
)
R
X
CI# clock period
LOW-level R
X
CI# clock pulse width
HIGH-level R
X
CI# clock pulse width
R
X
D setup time (R
X
C#)
R
X
D hold time (R
X
C#)
FD# output delay (R
X
C#)
Notes: 1. Interrupt timing due to R
X
RDY bit, receive errors (CRCER, OER, SFER), frame termination (EOF, ADET)
2. In LOOP mode: if NRZ or NRZI code, the minimum level is 8 t
CK
; if FM0, FM1, or Manchester code, the
minimum level is 12 t
CK
.
3. In LOOP mode: if NRZ or NRZI code, the minimum level is 3 t
CK
+40; if FM0, FM1, or Manchester code,
the minimum level is 5 t
CK
+40.
(Note 1)
ns
t
SRXCW
t
SRXCH
t
SRXDH
IRQ
t
SRXDH
t
SRXRDYI
FD#
R
X
D
R
X
CI, R
X
CO#
*
*
When FM0 and FM1 code, the first value of the data bit must be defined.
t
SRXDH
t
FD
t
SRXDS
t
SRXDS
t
SRXDS
t
SRXCL
*
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