![](http://datasheet.mmic.net.cn/120000/MB89P985PFV-201_datasheet_3559095/MB89P985PFV-201_23.png)
xix
Table 9.3-5
External Interrupt 1 Control Register (EIE1) Bits ..................................................................... 261
Table 9.4-1
Register and Vector Table for External Interrupt Circuit 1 Interrupts ....................................... 263
Table 10.3-1
External Interrupt Circuit 2 Pins ............................................................................................... 272
Table 10.3-2
External Interrupt 2 Control Register (EIE2) Bits vs. Pins ....................................................... 275
Table 10.3-3
External Interrupt 1 Control Register (EIE1) Bits ..................................................................... 276
Table 10.3-4
External Interrupt 1 Control Register (EIE1) Bits ..................................................................... 277
Table 10.4-1
Registers and Vector Table for External Interrupt Circuit 2 Interrupts ..................................... 278
Table 11.3-1
A/D Control Register 1 (ADC1) Bitss ....................................................................................... 292
Table 11.3-2
A/D Control Register 1 (ADC1) Bitss ....................................................................................... 295
Table 11.3-3
Example of ADCD Register Setting for Sense Function .......................................................... 296
Table 11.4-1
Register and Vector Table for A/D Converter Interrupt ........................................................... 297
Table 12.1-1
Watch Prescaler Interval Time ................................................................................................ 308
Table 12.1-2
Clocks Supplied by Watch Prescaler ....................................................................................... 309
Table 12.3-1
Watch Prescaler Control Register (WPCR) Bits ...................................................................... 313
Table 12.4-1
Register and Vector for Watch Prescaler Interrupt. ................................................................. 314
Table 13.1-1
Output Cycles and "H" Pulse Width Ranges ........................................................................... 322
Table 13.1-2
6-Bit PPG Resolution and Output Cycles (0.5 tinst count clock) ............................................. 324
Table 13.1-3
6-Bit PPG Resolution and Output Cycles (0.5 tinst count clock) ............................................. 325
Table 13.3-1
Remote Control Register 1 (RCR1) Bits .................................................................................. 332
Table 13.3-2
Remote Control Register 2 (RCR2) Bits .................................................................................. 334
Table 14.1-1
Bias and Duty Ratio Combinations .......................................................................................... 342
Table 14.2-1
LCD Drive Voltages and Biasing Modes ................................................................................. 348
Table 14.3-1
LCDC Control Register (LCR1) Bit Functions ......................................................................... 355
Table 14.3-2
LCD Control Register 2 (LCR2) Bit Functions ......................................................................... 357
Table 14.3-3
Segment Outputs, Display RAM Locations, and Sharing Port Pins ........................................ 359
Table 14.3-4
Common Outputs and Display RAM Bits Used in Each Duty Ratio Mode .............................. 359
Table 14.4-1
Display RAM Contents Example ............................................................................................. 362
Table 14.4-2
Display RAM Contents Example ............................................................................................. 365
Table 14.4-3
Display RAM Contents Example ............................................................................................. 368
Table 15.1-1
Output Frequency .................................................................................................................... 374
Table 15.4-1
Buzzer Register (BZCR) Bits ................................................................................................... 379
Table A-1
I/O Map .................................................................................................................................... 382
Table B.1-1
Instruction List Symbols ........................................................................................................... 386
Table B.1-2
Instruction List Columns .......................................................................................................... 387
Table B.2-1
Vector Table Address Corresponding to "vct" ......................................................................... 390
Table B.4-1
Transfer Instructions ................................................................................................................ 395
Table B.4-2
Arithmetic Opeation Instructions .............................................................................................. 399
Table B.4-3
Branch Instructions .................................................................................................................. 403