102
CHAPTER 3 CPU
3.7.3
Stop Mode
This section describes the operations of stop mode.
s Operation of Stop Mode
r Changing to stop mode
Stop mode the source oscillation. Almost functions stop while maintaining all register and RAM
contents at their value immediately before changing to stop mode.
If the system is in main clock mode, the main clock oscillation stops, but the subclock oscillation
continues to run. This means that the watch prescaler can still count and some functions that
run on the subclock can still function. Except the external interrupt circuit, however, the CPU
and other peripheral functions stop operating.
If the system is in subclock mode, both the main and subclock oscillations are stopped. All chip
functions other than external interrupt circuits stop. Accordingly, data can be held with minimum
power consumption.
Writing "1" to the stop bit in the standby control register (STBC: STP) changes the CPU to stop
mode. At this time, external pin states are held if the pin state specification bit (STBC: SPL) is
"0" If SPL is "1" external pins go to the high-impedance state. (Pins with the pull-up resistor
(optional) go to the "H" level.)
If an interrupt request is generated when "1" is written to the STP bit, the write to the bit is
ignored, and the CPU continues the instruction execution without change to stop mode. (The
CPU does not assume stop mode even after completion of the interrupt processing.)
Prohibit interrupt request out from the timebase timer (TBTC: TBIE = "0") before changing to
stop mode in main clock mode as necessary. Similarly, prohibita timeclock interrupt request
output from the watch prescaler (WPCR: WIE = "0") before changing to stop mode in subclock
mode.
r Wake-up from stop mode
A reset or an external interrupt wakes up the CPU from stop mode.
If reset occurs during stop mode on a product with power-on reset, the reset operation starts
after the main clock oscillation stabilization delay time. Products without power-on reset do not
require for the oscillation stabilization delay time after a reset in stop mode. The reset initializes
pin states.
If an interrupt request with an interrupt level higher than "11" occurs from an external interrupt
circuit during stop mode, the CPU wakes up from stop mode, regardless of the interrupt enable
flag (CCR: I) and interrupt level bits (CCR: IL1, IL0) in the CPU. Only external interrupt requests
can occur during stop mode because peripheral functions are stopped. In main-stop mode, the
watch prescaler operates, but it does not generate watch interrupts.
After wake-up from stop mode, the normal interrupt operation is performed after the oscillation
stabilization delay time has passed. If the interrupt request is accepted, the CPU executes
interrupt processing. If the interrupt request is not accepted, the CPU continues execution from
the subsequent instruction following the instruction executed immediately before entering stop
mode.