參數(shù)資料
型號： MB90234PFV-XXX
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 30/83頁
文件大?。?/td> 1566K
代理商： MB90234PFV-XXX
MB90230 Series
36
6. 16-bit I/O Timer
The 16-bit I/O timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules.
The 16-bit I/O timer can output six independent waveforms based on the 16-bit free run timer, allowing the input
pulse width and external clock cycle to be measured.
(1) Outline of Functions
16-bit free run timer (
× 1)
The 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. The value output
from this timer/counter is used as the base time by the input capture and output compare modules.
The counter operation clock cycle can be selected from the following four:
Four internal clock cycles (
φ/4, φ/16, φ/32, φ/64)
The interrupt counter value can be generated by compare/match operation with the overflow register and
compare register 0 (compare/match operation requires the mode setting).
The counter value can be initialized to “0000H” by compare/match operation with the reset register, software
clear register, and compare register 0.
Output compare module (
× 6)
The output compare module consists of six 16-bit compare registers, compare output latches, and control
registers. When the compare value matches the 16-bit free run timer value, this module can generates an
interrupt while inverting the output level.
Six compare registers can operate independently, and have each output pin and interrupt flag.
Two compare resisters can be used to control the same output pin.
The initial value for each output pin can be set.
The interrupt can be generated by compare/match operation.
Input capture module (
× 4)
The input capture module consists of four external input pins and associated capture and control registers. This
module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt
while holding the 16-bit free run timer value in the capture register.
The external input signal edge can be selected from the rising edge, failing edge or both edges.
Four input capture lines can operate independently.
The interrupts can be generated by a valid edge of external input signals. The extended intelligent I/O service
(EI2OS) can be activated.
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