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參數(shù)資料
| 型號(hào)： | MB90242A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 32 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, SQFP-80 |
| 文件頁(yè)數(shù)： | 200/258頁(yè) |
| 文件大?。?/td> | 2010K |
| 代理商： | MB90242A |
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2.1 CPU
41
2.1.4 Interrupts, Expanded Intelligent I/O Services, and Exceptions
The F2MC-16F CPU has four types of functions capable of reacting to the occurrence of a particular event,
interrupting the execution of the instruction that is currently being processed, and transferring control to a
separately defined program.
Hardware interrupts ................................................. Interrupt processing triggered by events occurring
in internal resources.
Software interrupts .................................................. Interrupt processing triggered by software instruc-
tions that generate specific events.
Expanded intelligent I/O services (EI2OS) ............. Transfer processing triggered by events occurring
in internal resources.
Exceptions ............................................................... Processing interruptions triggered by the occur-
rence of abnormal circumstances.
Hardware Interrupts
(1) Overview
In a hardware interrupt, the CPU reacts to an interrupt request signal from its internal resources circuit,
temporarily suspends the execution of the program that it has been executing, and transfers control to an
interrupt processing program defined by the user.
Hardware interrupts are initiated when the level of the interrupt request is compared with the interrupt
level mask (ILM) register in the CPU processor status (PS) register, and the contents of the I flag in the
PS register are referenced by hardware, in order to determine that interrupt conditions exist. When a
hardware interrupt is generated, the CPU performs interrupt processing as follows.
The contents of the A, DPR, ADB, DTB, PCB, PC and PS registers in the CPU are saved to the sys-
tem stack.
The level of the current interrupt request is stored in the ILM register field in the PS register.
The CPU branches to the corresponding interrupt vector.
(2) Configuration
Three areas of the F2MC-16F core are involved in hardware interrupt processing.
Internal resources ... The interrupt enable bit and interrupt request bit are used as reference to control
interrupt requests from internal resources.
Interrupt controller ... The ICR register assigns interrupt priority levels and determines priority of
interrupts occurring at the same time.
CPU ... The I and ILM registers compare the level of the interrupt request with the level of the exist-
ing requests and identify an interrupt enable status.
The microcode function executes the necessary steps in interrupt processing.
Each of these functions is realized through register settings -- the internal resource control registers for
the internal resources, the ICR register for the interrupt controller, and the CCR register for the CPU.
Before a hardware interrupt can be used, therefore, settings must be made to these three locations. For
information about the ICR register, see 'Interrupt Control Register (ICR)' in the section "Expanded
Intelligent I/O Services."
The interrupt vector tables referred to during interrupt processing are located in memory area FFFC00H
to FFFFFFH, and the same tables are used for software interrupts. Table 2.1.12 lists interrupt numbers
and interrupt vectors assigned.
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