2.1 CPU
54
Chapter 2: Hardware
s Exception Processing
The F2MC-16L core provides exception processing for exceptions arising from the following causes.
(1) Execution of undefined instructions
Exception processing is fundamentally the same as interrupt processing, in that exception processing
departs from normal processing at the point where the occurrence of an abnormal condition is detected
at the boundary between instructions. In general, exception processing occurs as a result of an
unexpected operation, and its use is recommended only in debugging or for startup of recovery software
in emergency situations.
s Exceptions Occurring from Execution of Undefined Commands
The F2MC-16L considers all codes not defined on the instruction map to be undefined instructions.
Execution of undefined instructions is handled as the equivalent of the software interrupt instruction
‘INT 10.’ This means that after the contents of the AL, AH, DPR, DTB, ADB, PCB, PC and PS
registers are saved to the system stack, the I flag is set to ‘0,’ the S flag is set to ‘1’ and the program
branches to the vector indicated by interrupt number 10. The value of register PC that is saved to the
stack will be the address containing the undefined instruction. For this reason, recovery using the RETI
instruction is possible but meaningless since another exception will occur immediately.
2.1.5 Standby Control Register Access
The MB90660A series microcontroller can be placed in any of its low-power consumption modes (stop
mode and sleep mode) by writing to the power saving mode control register, provided that the instructions
used are those shown in Table 2.1.16. Note however that operation of the MB90660A series
microcontroller is not warranted if instructions other than those listed in Table 2.1.16 are used to place the
chip in low-power consumption modes. When the low-power consumption mode control register is used to
control functions other than change to low-power consumption modes, any instructions may be used.
When using word-length values to write to the low-power consumption mode control register, be sure to
write to even numbered addresses. Attempting transition to low-power consumption modes by writing to
odd numbered addresses may cause abnormal operation.
Table 2.1.16 Commands Used for Transition To Low-power Consumption Modes
MOV
io,#imm8
MOV
dir,#imm8
MOV
eam,#imm8
MOV
eam,Ri
MOV
io,A
MOV
dir,A
MOV
addr16,A
MOV
eam,A
MOV
@RLi+disp8,A
MOVP addr24,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
MOVW @RLi+disp8,A
MOVPWaddr24,A
SETB io:bp
SETB dir:bp
SETB addr16:bp