2.5 UART
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(3) Asynchronous (Start-Stop Synchronized) Mode
a) Transfer Data Format
The UART handles only data in NRZ (non-return to zero) format. Figure 2.5.2 shows the data
format.
Fig. 2.5.2 Transfer Data Format (Modes, 0, 1)
As shown in Figure 2.5.2, transfer data always begins with a start bit (‘L’ level data value), followed
by the transfer data at the designated bit-length, and ends with a stop bit (‘H’ level data value).
When an external clock signal is selected, the clock should be input at all times.
In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor
mode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multi-processor
mode. However, an A/D bit must be attached.
b) Receiving Operation
Whenever the RXE bit (bit 9) in the SCR register is set to ‘1’ the UART is receiving.
The appearance of a start bit on the receiving line allows one frame of data to be received according
to the data format determined by the SCR register. When one frame of data has been received, error
flags will be set if the corresonding errors have occurred, and then the RDRF flag (SSR register bit
12) will be set. At this time if the RIE bit (bit 9) in the SSR register is set to ‘1’ a receiving interrupt
will be sent to the CPU. The CPU will check each of the flags in the SSR register and read the SIDR
register if data has been received normally. If any errors have occured, the necessary processing
should be followed.
The RDRF flag is cleared when the SIDR register is read.
c) Sending Operation
Whenever the TDRE flag (bit 11) in the SSR register is set to ‘1’ the UART is writing outgoing data
to the SODR register. If the TXE bit (bit 8) is set to ‘1’ sending is in progress.
The TDRE flag is reset as soon as data placed in the SODR register starts to be transferred to the
sending shift register for transmission. This enables the next unit of outging data to be placed in the
SODR register. At this time if the TIE bit (bit 8) in the SSR register is set to ‘1’ a transmission
interrupt is sent to the CPU, causing outgoing data to be placed into the SODR register.
The TDRE flag is momentarily cleared each time data is placed into the SODR register.
0
1
0
1
0
1
0
1
Start LSB
MSB Stop........(mode 0)
A/D Stop........(mode 1)
SIN,SOT
Transfer data value: 01001101B