參數(shù)資料
型號: MB91121PFV
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120
封裝: PLASTIC, LQFP-120
文件頁數(shù): 48/100頁
文件大?。?/td> 2316K
代理商: MB91121PFV
MB91121 Series
DS07-16303-4E
51
9.
Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
Block diagram
LEVEL0 4
IM
INT0 2
OR
NMI
RI00
RI47
(DLYIRQ)
DLYI 1
ICR00
ICR47
4
5
6
LEVEL4 to
HLDCAN 3
VCT0 5
VCT5 to
R-bus
Priority judgment
NMI processing
Level judgment
Vector judgment
Level
vector
generation
HLDREQ
cancel
request
*1 : DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section
“11. Delayed Interrupt Module” for detail) .
*2 : INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3 : HLDCAN is a bus release request signal for bus masters other than CPU.
*4 : LEVEL5 to LEVEL0 are interrupt level outputs.
*5 : VCT5 to VCT0 are interrupt vector outputs.
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