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參數(shù)資料
| 型號： | MB91121PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 79/100頁 |
| 文件大?。?/td> | 2316K |
| 代理商： | MB91121PFV |
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MB91121 Series
8
DS07-16303-4E
47
DACK1/PE5
F
[DACK1] DMAC external transfer request acknowledge output
(ch.1) . This function is enabled with the DMAC transfer request
acknowledge output flag set to “Enabled”.
[PE5] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to “Disabled”.
48
EOP1/PE6
F
[EOP1] DMAC EOP output (ch.1) . This function is enabled with
the EOP output flag set to “Enabled”.
[PE6] General-purpose I/O port
49
DREQ2/PE7
F
[DREQ2] DMA external transfer request input (ch.2) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.
[PE7] General-purpose I/O port
50
DACK2/PI0
F
[DACK2] DMAC external transfer request acknowledge output
(ch.2) . This function is enabled with the DMAC transfer request
acknowledge output flag set to “Enabled”.
[PI0] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to "Disabled".
51
EOP2/ATG/PI1
F
[EOP2] DMAC EOP output (ch.2) . This function is enabled with
the EOP output flag set to “Enabled”.
[ATG] A/D converter external trigger input. Since this input is used
whenever the A/D converter external trigger signal has been se-
lected as an A/D trigger event, the output by the other function
must remain off unless used intentionally.
[PI1] General-purpose I/O port. This function is enabled with the
DMAC transfer termination signal output flag set to “Disabled”.
53
54
X1
X0
A
Clock (oscillation) output.
Clock (oscillation) input.
56
57
58
59
60
RAS0/PB0
CS0L/PB1
CS0H/PB2
DW0/PB3
RAS1/PB4
F
RAS output of DRAM bank 0
CASL output of DRAM bank 0
CASH output of DRAM bank 0
WE output of DRAM bank 0 (Low active)
RAS output of DRAM bank 1
[PB0 to PB3] Can serve as a port when not used for signal output.
61
62
63
CS1L/PB5
CS1H/PB6
DW1/PB7
F
CASL output of DRAM bank 1
CASH output of DRAM bank 1
WE output of DRAM bank 1 (Low active)
[PB5 to PB7] Can serve as a port when not used for signal output.
65
CS0
M
Chip select 0 output (Low active) .
(Continued)
Pin no.
Pin name
Circuit type
Function
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