參數(shù)資料
型號(hào)： MB91121PFV
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁(yè)數(shù)： 68/100頁(yè)
文件大?。?/td> 2316K
代理商： MB91121PFV
MB91121 Series
DS07-16303-4E
7
37
SI1/PF3
F
[SI1] UART1 data input. Since this input is used whenever
UART1 is in input operation, the output by the other function must
remain off unless used intentionally.
[PF3] General-purpose I/O port
38
SO1/PF4
F
[SO1] UART1 data output. This function is enabled with the
UART1 data output flag set to “Enabled”.
[PF4] General-purpose I/O port. This function is enabled with the
UART1 data output flag set to “Disabled”.
39
SC1/PF5
F
[SC1] UART1 clock input/output. The clock output is enabled with
the UART1 clock output flag set to “Enabled”.
[PF5] General-purpose I/O port. This function is enabled with the
UART1 clock output flag set to “Disabled”.
40
SI2/PF6
F
[SI2] UART2 data input. Since this input is used whenever
UART2 is in input operation, the output by the other function must
remain off unless used intentionally.
[PF6] General-purpose I/O port
41
SO2/PF7
F
[SO2] UART2 data output. This function is enabled with the
UART2 data output flag set to “Enabled”.
[PF7] General-purpose I/O port. This function is enabled with the
UART2 data output flag set to “Disabled”.
42
SC2/PE0
F
[SC2] UART2 clock input/output. The clock output is enabled with
the UART2 clock output flag set to “Enabled”.
[PE0] General-purpose I/O port. This function is enabled with the
UART2 clock output flag set to “Disabled”.
43
DREQ0/PE1
F
[DREQ0] DMA external transfer request input (ch.0) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.
[PE1] General-purpose I/O port
44
DACK0/PE2
F
[DACK0] DMAC external transfer request acknowledge output
(ch.0) . This function is enabled with the DMAC transfer request
acknowledge output flag set to “Enabled”.
[PE2] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to “Disabled”.
45
EOP0/PE3
F
[EOP0] DMAC EOP output (ch.0) . This function is enabled with
the EOP output flag set to “Enabled”.
[PE3] General-purpose I/O port
46
DREQ1/PE4
F
[DREQ1] DMA external transfer request input (ch.1) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.
[PE4] General-purpose I/O port
(Continued)
Pin no.
Pin name
Circuit type
Function
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