參數(shù)資料
型號(hào): MBM29DL64DF-70
廠商: Fujitsu Limited
英文描述: FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT
中文描述: 閃存的CMOS 64米(8的MX 8 / 4的MX 16)位
文件頁(yè)數(shù): 36/68頁(yè)
文件大?。?/td> 854K
代理商: MBM29DL64DF-70
MBM29DL64DF
-70
36
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, determines whether the device is in the Embedded Erase Algorithm or in Erase
Suspend.
Successive reads from the erasing sector causes DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector causes DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from
the non-erase
suspended sector indicates a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. These two status bits, along with that of DQ
7
, operate as follows :
For example DQ
2
and DQ
6
determine if the erase-suspend-read mode is in progress. (DQ
2
toggles while DQ
6
does not.) See also “Toggle Bit Status” table and “DQ
2
vs.DQ
6
” waveform.
Furthermore DQ
2
determines which sector is being erased. At the erase mode, DQ
2
toggles if this bit is read
from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row
to determine whether a toggle bit is on. Typically the system would note and store the value of the toggle bit
after the first read. After the second read, the system compares the new value of the toggle bit with the first. If
the toggle bit is not toggling, this indicates that the device completes the program or erase operation. The system
reads array data on DQ
7
to DQ
0
on the following read cycle.
However if after the initial two read cycles, the system determines that the toggle bit is still on, the system also
should note whether the value of DQ
5
is high (see the section on “DQ
5
”) . If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high.
If the toggle bit is no longer toggling, the device successfully completes the program or erase operation. If it is
still toggling, the device does not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
5
has not
gone high. The system continues to monitor the toggle bit and DQ
5
through successive read cycles, determining
the status as described in the previous paragraph. Alternatively the system chooses to perform other system
tasks. In this case the system must start at the beginning of the algorithm to determine the status of the operation.
Toggle Bit Status Table
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
2
to toggle.
*2 : Reading from the non-erase suspend sector address indicates logic “1” at the DQ
2
bit.
RY/BY
Ready/Busy
The device provides a RY/BY open-drain output pin as a way to indicate that Embedded Algorithms are either
in progress or have been completed. When output is low the device is busy with either a program or erase
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle*
1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1*
2
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