參數(shù)資料
型號(hào): MBM29DL64DF-70
廠商: Fujitsu Limited
英文描述: FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT
中文描述: 閃存的CMOS 64米(8的MX 8 / 4的MX 16)位
文件頁數(shù): 37/68頁
文件大?。?/td> 854K
代理商: MBM29DL64DF-70
MBM29DL64DF
-70
37
operation. If output is high, the device is ready to accept any read/write or erase operation. If the device is placed
in an Erase Suspend mode, RY/BY output is high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin indicates busy
condition during RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram” and “(11) RESET, RY/BY Timing Diagram” in
I
TIMING DIAGRAM. RY/BY pin is pulled high in standby
mode.
Since this is an open-drain output, Pull-up resistor needs to be connected to V
CC
; multiples of devices may be
connected to the host system via more than one RY/BY pin in parallel.
Data Protection
The device offers protection against accidental erasure or programming caused by spurious system level signals
that may exist during power transitions. During power-up the device automatically resets the internal state
machine in Read mode. With its control register architecture, alteration of memory contents only occurs after
successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, the write cycle is locked out for V
CC
less
than V
LKO
. If V
CC
<
V
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device resets to the read mode. Subsequent writes are ignored until the V
CC
level goes
higher than V
LKO
. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when V
CC
is above V
LKO
.
If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE or WE does not initiate write cycle.
Logical Inhibit
Writing is prohibited by holding any one of OE
=
V
IL
, CE
=
V
IH
or WE
=
V
IH
. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE
=
CE
=
V
IL
and OE
=
V
IH
does not accept commands on the rising edge of WE.
Internal state machine is automatically reset to the read mode on power-up.
Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both program and erase command that are addressed to protect sectors. Any commands to program or erase
addressed to protected sector are ignored (see
I
FUNCTIONAL DESCRIPTION, Sector Group Protection) .
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