參數(shù)資料
型號： MBM29F002T
廠商： Fujitsu Limited
英文描述： 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器)
中文描述： 200萬（256K × 8）位快閃記憶體（單5V的電源電壓256K × 8位閃速存儲器）
文件頁數(shù)： 15/52頁
文件大?。?/td> 591K
代理商： MBM29F002T
15
MBM29F002T/002B/002ST/002SB
-70/-90/-12
Notes:
1. Address bits A
15
to A
17
= X = H or L for all address commands except for Program Address (PA) and Sector
Address (SA).
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A
17
, A
16
, A
15
, A
14
, and A
13
will uniquely select
any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.
* :Either of the two reset commands will reset the device.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to read
mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase
Resume (30H) commands are valid only while the sector Erase operation is in progress. Moreover both Read/
Reset commands are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Table 6 MBM29F002T/002B/002ST/002SB Command Definitions
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read/Reset*
1
XXXXH
F0H
—
—
—
—
—
—
—
—
—
—
Read/Reset*
3
5555H AAH
2AAAH
55H 5555H F0H
RA
RD
—
—
—
—
Autoselect
3
5555H AAH
2AAAH
55H 5555H 90H
—
—
—
—
—
—
Byte Program
4
5555H AAH
2AAAH
55H 5555H A0H
PA
PD
—
—
—
—
Chip Erase
6
5555H AAH
2AAAH
55H 5555H 80H 5555H AAH
2AAAH
55H 5555H 10H
Sector Erase
6
5555H AAH
2AAAH
55H 5555H 80H 5555H AAH
2AAAH
55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Addr (H or L). Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Addr (H or L). Data (30H)
相關PDF資料
PDF描述
MBM29F016-12 CMOS 16M (2M x 8) Bit Flash Memory(CMOS 16M (2M x 8)位閃速存儲器)
MBM29F016-90 CMOS 16M (2M x 8) Bit Flash Memory(CMOS 16M (2M x 8)位閃速存儲器)
MBM29F016A 16M (2M X 8) BIT
MBM29F016A-12 1.65A, 2.7-5.5V Single Hot-Swap IC Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC -40 to 85
MBM29F016A-12PFTN 16M (2M X 8) BIT
相關代理商/技術參數(shù)
參數(shù)描述
MBM29F002T-90PD# 制造商:FUJITSU 功能描述:
MBM29F002TC 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT
MBM29F002TC-55 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT
MBM29F002TC-70 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT
MBM29F002TC-90 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*