參數(shù)資料
型號: MBM29F200TC-70PFTR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: Dual, Current-Limited, Power-Distribution Switches 8-SOIC -40 to 85
中文描述: 128K X 16 FLASH 5V PROM, 70 ns, PDSO48
封裝: PLASTIC, REVERSE, TSOP1-48
文件頁數(shù): 21/48頁
文件大小: 508K
代理商: MBM29F200TC-70PFTR
21
MBM29F200TC
-55/-70/-90
/MBM29F200BC
-55/-70/-90
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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