參數(shù)資料
型號: MBM29F400BA
廠商: Fujitsu Limited
英文描述: 4M (512K×8/256K ×16) Bit Flash Memory(4M 單5V 電源電壓512K×8/256K ×16位閃速存儲器)
中文描述: 4分(為512k × 8/256K × 16)位閃存(4分單5V的電源電壓為512k × 8/256K × 16位閃速存儲器)
文件頁數(shù): 19/47頁
文件大?。?/td> 424K
代理商: MBM29F400BA
19
MBM29F400TA/MBM29F400BA
If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may
not be reused. However, other sectors are still functional and may be used for the program or erase operation.
The device must be reset to use other sectors. Write the Reset command sequence to the device, and then
execute program or erase command sequence. This allows the system to continue to use the other active sectors
in the device.
If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination
of sectors are bad.
If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing
that byte is bad and this sector may not be reused. (Other sectors are still functional and can be reused.)
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing limits, the
DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
used.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence, the sector erase time-out will begin. DQ
3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ
3
may be
used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation
is completed as indicated by Data Polling or Toggle Bit. If DQ
3
is low (“0”), the device will accept additional sector
erase commands. To insure the command has been accepted, the system software should check the status of
DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status
check, the command may not have been accepted.
Refer to Table 8: Hardware Sequence Flags.
RY/BY
Ready/Busy
The MBM29F400TA/BA provides a RY/BY output pin as a way to indicate to the host system that the Embedded
TM
Algorithms are either in progress or completed. If the output is low, the device is busy with either a program or
erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the
RY/BY pin is low, the device will not accept any additional program or erase commands. If the MBM29F400TA/
BA is placed in an Erase Suspend mode, the RY/BY output will be high. Also, since this is an open drain output,
many RY/BY pins can be tied together in parallel with a pull up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse in the four write
pulse sequence. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE
pulse in the six write pulse sequence. The RY/BY pin should be ignored while RESET pin is at V
IL
.
Refer to Figure 10, 11 for a detailed timing diagram.
相關(guān)PDF資料
PDF描述
MBM29F400TA 4M (512K×8/256K ×16) Bit Flash Memory(4M 單5V 電源電壓512K×8/256K ×16位閃速存儲器)
MBM29F400TC-90PFTN Quad Current-Limited Power Distribution Switches 16-SOIC -40 to 85
MBM29F400BC-55 PP75-180-RETAINING PIN RoHS Compliant: Yes
MBM29F400BC-55PF Cable clamp hardware pak, 20 A, black, clamp termination, for plug, 4 pole
MBM29F400BC-55PFTN PP10 PIN CNT #10 TIN
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