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參數(shù)資料
| 型號： | MBM29F400TA |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M (512K×8/256K ×16) Bit Flash Memory(4M 單5V 電源電壓512K×8/256K ×16位閃速存儲器) |
| 中文描述： | 4分（為512k × 8/256K × 16）位閃存（4分單5V的電源電壓為512k × 8/256K × 16位閃速存儲器） |
| 文件頁數(shù)： | 20/47頁 |
| 文件大?。?/td> | 424K |
| 代理商： | MBM29F400TA |
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20
MBM29F400TA/MBM29F400BA
RESET
Hardware Reset
The MBM29F400TA/BA device may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
20
μ
s after the RESET pin is driven low. (Furthermore, once the RESET pin goes high, the device requires an
additional 50 ns before it will allow read access.) When the RESET pin is low, the device will be in the standby
mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during
a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY
output signal should be ignored during the RESET pulse. Refer to Figure 11 for the timing diagram. Refer to
Temporary Sector Unprotection for additional functionality.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TA/BA device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
0
to
DQ
15
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tristated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to Figures 12 and 13 for the timing diagram.
Data Protection
The MBM29F400TA/BA is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F400TC-90PFTN | Quad Current-Limited Power Distribution Switches 16-SOIC -40 to 85 |
| MBM29F400BC-55 | PP75-180-RETAINING PIN RoHS Compliant: Yes |
| MBM29F400BC-55PF | Cable clamp hardware pak, 20 A, black, clamp termination, for plug, 4 pole |
| MBM29F400BC-55PFTN | PP10 PIN CNT #10 TIN |
| MBM29F400BC-55PFTR | 4M (512K X 8/256K X 16) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F400TC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29F400TC-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29F400TC-55PF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29F400TC-55PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4M (512K x 8/256K x 16) BIT |
| MBM29F400TC-55PFTR | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4M (512K x 8/256K x 16) BIT |
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