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參數(shù)資料
| 型號(hào)： | MBM29LV080-12 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8M (1M ×8) Bit Flash Memory(8M (1M ×8)位 單5V 電源電壓閃速存儲(chǔ)器) |
| 中文描述： | 8米（1米× 8）位閃存（8米（1米× 8）位單5V的電源電壓閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MBM29LV080-12 |
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18
MBM29LV080
-10/-12/-15
RY/BY
Ready/Busy
The MBM29LV080 provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded
Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program
or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the
RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the
Erase Suspend command. If the MBM29LV080 is placed in an Erase Suspend mode, the RY/BY output will be high,
by means of connecting with a pull-up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during RESET pulse. Refer to Figure 12 for a detailed timing diagram. The RY/BY pin is pulled high
in standby mode.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Data Protection
The MBM29LV080 is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets the
internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents
only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up and
power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
or WE = V
IH
. To initiate a write cycle and must be a
logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE =V
IL
and OE = V
IH
will not accept commands on the rising edge of WE. The
internal state machine is automatically reset to the read mode on power-up.
Sector Protection
MBM29LV080 features hardware sector protection sector by sector at the user's site. This feature will disable both
programing to protected sector and erase operations.
This feature ignores programming to protected sector and erase operation.
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| MBM29LV080A-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M x 8) BIT |
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