參數(shù)資料
型號： MBM29PDS322BE10PBT
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： NEOZED TYPE,400V.10A
中文描述： 2M X 16 FLASH 1.8V PROM, 100 ns, PBGA63
封裝： PLASTIC, FBGA-63
文件頁數(shù)： 32/66頁
文件大?。?/td> 694K
代理商： MBM29PDS322BE10PBT
MBM29PDS322TE/BE
10/11
32
Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row to
determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
7
to DQ
0
on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
5
is high (see the section on DQ
5
). If it is the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
5
has not
gone high. The system may continue to monitor the toggle bit and DQ
5
through successive read cycles, deter-
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status
of the operation. (Refer to Figure 23.)
Table 10 Toggle Bit Status
DQ
7
Note
Successive reads from the erasing or erase-suspend sector will cause DQ
2
to toggle. Reading from non-
erase suspend sector address will indicate logic “1” at the DQ
2
bit.
RY/BY
Ready/Busy
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded
Algorithms are either in progress or has been completed. If output is low, device is busy with either a program
or erase operation. If output is high, device is ready to accept any read/write or erase operation. If the device is
placed in an Erase Suspend mode, RY/BY output will be high.
During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy
condition during RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. RY/BY pin is pulled
high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Mode
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1 (Note)
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