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| 型號(hào)： | MBM29PDS322BE10PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | NEOZED TYPE,400V.10A |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 100 ns, PBGA63 |
| 封裝： | PLASTIC, FBGA-63 |
| 文件頁(yè)數(shù)： | 33/66頁(yè) |
| 文件大?。?/td> | 694K |
| 代理商： | MBM29PDS322BE10PBT |
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MBM29PDS322TE/BE
10/11
33
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up device automatically resets internal state
machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs
after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Power On/Off Timing
The RESET pin must be held low during V
CC
ramp up to insure that device power up correctly.
(Refer to Figure 5.3.)
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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