參數(shù)資料
型號: MC13211
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: ZigBee- Compliant Platform - 2.4 GHz Low Power Transceiver for the IEEE 802.15.4 Standard plus Microcontroller(ZigBee平臺- 為IEEE 802.15.4標準和微控制器設(shè)計的2.4 GHz低功率收發(fā)器)
中文描述: ZigBee兼容平臺- 2.4 GHz的低功耗收發(fā)器符合IEEE 802.15.4標準加微控制器(ZigBee的平臺-為IEEE 802.15.4無線標準和微控制器設(shè)計的2.4 GHz的低功率收發(fā)器)
文件頁數(shù): 55/70頁
文件大?。?/td> 802K
代理商: MC13211
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor
55
Table 14. ATD Timing/Performance Characteristics
1
1
All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and
that adequate low-pass filtering is present on analog input pins (filter with 0.01
μ
F to 0.1
μ
F capacitor between analog input
and V
REFL
). Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which
will vary based on board layout and the type and magnitude of the activity.
2
This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single
conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting
the conversion and setting the CCF flag. The total conversion time in Bus Cycles for a conversion is:
SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2 CC Bus Cycles = ((PRS+1)*2) * (28)
3
R
AS
is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may not
fully charge the input circuitry of the ATD resulting in accuracy error.
4
Analog input must be between V
REFL
and V
REFH
for valid conversion. Values greater than V
REFH
will convert to $3FF less the
full scale error (E
FS
).
5
The resolution is the ideal step size or 1LSB = (V
REFH
–V
REFL
)/1024
6
Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code
width is the difference in the transition voltages to and from the current code.
7
Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition
voltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((V
REFH
+E
FS
)–(V
REFL
+E
ZS
))).
8
Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal
transition voltage to a given code is (Code–1/2)*(1/(V
REFH
–V
REFL
)).
9
Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal
transition voltage to a given code is (Code–1/2)*(1/(V
REFH
–V
REFL
)).
10
Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin.
Reducing the impedance of the network reduces this error.
Num
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
1
ATD conversion clock
frequency
f
ATDCLK
2.08V < V
DDAD
< 3.6V
0.5
2.0
MHz
1.80V < V
DDAD
< 2.08V
0.5
1.0
2
Conversion cycles
(continuous convert)
2
CCP
28
28
<30
ATDCLK
cycles
3
Conversion time
T
conv
2.08V < V
DDAD
< 3.6V
14.0
60.0
μ
S
1.80V < V
DDAD
< 2.08V
28.0
60.0
4
Source impedance at
input
3
R
AS
10
k
5
Analog Input Voltage
4
V
AIN
V
REFL
V
REFH
V
6
Ideal resolution (1 LSB)
5
RES
2.08V < V
DDAD
< 3.6V
2.031
3.516
mV
1.80V < V
DDAD
< 2.08V
1.758
2.031
7
Differential non-linearity
6
DNL
1.80V < V
DDAD
< 3.6V
+0.5
+1.0
LSB
8
Integral non-linearity
7
INL
1.80 V < V
DDAD
< 3.6V
+0.5
+1.0
LSB
9
Zero-scale error
8
E
ZS
1.80V < V
DDAD
< 3.6V
+0.4
+1.0
LSB
10
Full-scale error
9
E
FS
1.80V < V
DDAD
< 3.6V
+0.4
+1.0
LSB
11
Input leakage error
10
E
IL
1.80V < V
DDAD
< 3.6V
+0.05
+5
LSB
12
Total unadjusted
error
11
E
TU
1.80V < V
DDAD
< 3.6V
+1.1
+2.5
LSB
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