參數(shù)資料
型號(hào): MC33298
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Eight Output Switch with Serial Peripheral Interface I/O(帶SPI接口的八輸出開關(guān))
中文描述: 8個(gè)串行外圍接口的I / O(帶的SPI接口的八輸出開關(guān)輸出開關(guān))
文件頁(yè)數(shù): 10/28頁(yè)
文件大?。?/td> 642K
代理商: MC33298
33298
10
Go to: www.freescale.com
.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V
V
DD
5.5 V, 9.0 V
V
PWR
16 V, -40
°
C
T
A
125
°
C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Interface Timing
SCLK Clock Period (Note 33)
t
pSCLK
500
ns
SCLK Clock High Time
t
wSCLKH
175
ns
SCLK Clock Low Time
t
wSCLKL
175
ns
Required Low State Duration for Reset (V
IL
< 0.2 VDD) (Note 34)
t
w(RST)
250
50
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t
LEAD
250
50
ns
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
t
LAG
250
50
ns
SI to Falling Edge of SCLK (Required for Setup Time)
t
SISU
125
25
ns
Falling Edge of SCLK to SI (Required for Hold Time)
t
SI(HOLD)
125
25
ns
SO Rise Time (C
L
= 200 pF)
t
rSO
25
75
ns
SO Fall Time (C
L
= 200 pF)
t
fSO
25
75
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 35)
t
rSI
200
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 35)
t
fSI
200
ns
Time from Falling Edge of CS to SO Low Impedance (Note 36)
t
SO(EN)
200
ns
Time from Rising Edge of CS to SO High Impedance (Note 37)
t
SO(DIS)
200
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 38)
0.2 V
DD
< SO > 0.8 V
DD
, C
L
= 200 pF
t
VALID
50
125
ns
Notes:
33.
34.
35.
36.
37.
38.
Clock period include 75 ns rise plus 75 ns fall transition in addition to clock high and low time.
RST Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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