MC33888FB
PINS FUNCTION DESCRIPTION
Quad High Side and Octal Low Side Switch for Automotive
3
Pin Number
pin name
Description
6,9,12,15
GND
Ground. These pins serve as the ground for the source of the low-side output tran-
sistors as well as the logic portion of the device.
4
VPWR
Battery Voltage
43-49
36-42
HS0
HS1
Each pin is the source of a 10m Ohm FET, high-side driver, which delivers current
through the connected loads. These outputs can be controlled via SPI or using the
IHS pins depending on the internal configuration. These outputs are current limited
and thermally protected. During failsafe mode, output HS0 will be turned on until the
device is reinitialized and then immediately followed by normal operation.
56, 57
28, 29
HS2
HS3
Each pin is the source of a 40m Ohm FET, high-side driver which delivers current
through the connected loads. These outputs can be controlled via SPI or using the
IHS pins depending on the internal configuration. These outputs are current limited
and thermally protected. During failsafe mode, output HS2 will be turned on until the
device is reinitialized and then immediately followed by normal operation.
61
62
24
23
IHS0
IHS1
IHS2
IHS3
Each High-Side Input pin is used to directly control only one designated HSO out-
put. These inputs may or may not be activated depending upon the configured state
of the internal logic.
60
25
CSNS0-1,
CSNS2-3
The Current Sense pins deliver a ratioed amount of the high-side output currents
that can be used to generate signal ground referenced output voltages for use by the
microcontroller. Each respective CSNS pin can be configured via SPI to deliver cur-
rent from either of the two assigned outputs, or the currents could be the sum of the
two. Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2
and/or HS3 are sensed via CSNS2-3.
5
8
11
14
LS4
LS6
LS8
LS10
Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through
the connected loads. Each of the outputs are actively clamped at 53V. These out-
puts are current and thermal overload protected. Maximum steady state current
through each of these outputs is 500mA.
7
10
13
16
LS5
LS7
LS9
LS11
Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through
the connected loads. Each of the outputs are actively clamped at 53V. These out-
puts are current and thermal overload protected. Maximum steady state current
through each of these outputs is 800mA
22
ILS
The low-side input pin is used to directly control a number of the low-side devices as
configured by SPI. This pin may or may not be activated depending upon the config-
ured state of the internal logic.
20
SCLK
The Serial Clock Pin is connected to the SCLK pin of the master device which is a
bit (shift) clock for the SPI port. It transitions 1 time per bit transferred at an operat-
ing frequency, fSPI and is idle between command transfers. It is 50% duty cycle,
and has CMOS logic levels. This signal is used to shift data to and from the device..
21
SI
The Serial Input is connected to the SPI Serial Data Output pin of the master device
from which it receives output command data. This input has an internal active pull-
down and requires CMOS logic levels. The serial data transmitted on this line is a 16
bit control command sent MSB first, which controls the twelve output channels. Bits
D0-D3 control the high-side outputs HS0-HS3, respectively. Bits D4-D11 control the
low-side outputs LS4-LS11, respectively. The master will ensure that data is avail-
able on the falling edge of SCLK.
F
Freescale Semiconductor, Inc.
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