Chapter 1 Device Overview MC9S12XE-Family
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
81
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Table 1-14. Interrupt Vector Locations (Sheet 1 of 4)
Vector Address(1)
XGATE
Channel
ID(2)
Interrupt Source
CCR
Mask
Local Enable
STOP
Wake up
WAIT
Wake up
Vector base + $F8
—
Unimplemented instruction trap
None
—
Vector base+ $F6
—
SWI
None
—
Vector base+ $F4
—
XIRQ
X Bit
None
Yes
Vector base+ $F2
—
IRQ
I bit
IRQCR (IRQEN)
Yes
Vector base+ $F0
$78
Real time interrupt
I bit
CRGINT (RTIE)
Refer to CRG
interrupt section
Vector base+ $EE
$77
Enhanced capture timer channel 0
I bit
TIE (C0I)
No
Yes
Vector base + $EC
$76
Enhanced capture timer channel 1
I bit
TIE (C1I)
No
Yes
Vector base+ $EA
$75
Enhanced capture timer channel 2
I bit
TIE (C2I)
No
Yes
Vector base+ $E8
$74
Enhanced capture timer channel 3
I bit
TIE (C3I)
No
Yes
Vector base+ $E6
$73
Enhanced capture timer channel 4
I bit
TIE (C4I)
No
Yes
Vector base+ $E4
$72
Enhanced capture timer channel 5
I bit
TIE (C5I)
No
Yes
Vector base + $E2
$71
Enhanced capture timer channel 6
I bit
TIE (C6I)
No
Yes
Vector base+ $E0
$70
Enhanced capture timer channel 7
I bit
TIE (C7I)
No
Yes
Vector base+ $DE
$6F
Enhanced capture timer overow
I bit
TSRC2 (TOF)
No
Yes
Vector base+ $DC
$6E
Pulse accumulator A overow
I bit
PACTL (PAOVI)
No
Yes
Vector base + $DA
$6D
Pulse accumulator input edge
I bit
PACTL (PAI)
No
Yes
Vector base + $D8
$6C
SPI0
I bit
SPI0CR1
(SPIE, SPTIE)
No
Yes
Vector base+ $D6
$6B
SCI0
I bit
SCI0CR2
(TIE, TCIE, RIE, ILIE)
Yes
Vector base + $D4
$6A
SCI1
I bit
SCI1CR2
(TIE, TCIE, RIE, ILIE)
Yes
Vector base + $D2
$69
ATD0
I bit
ATD0CTL2 (ASCIE)
Yes
Vector base + $D0
$68
ATD1
I bit
ATD1CTL2 (ASCIE)
Yes
Vector base + $CE
$67
Port J
I bit
PIEJ (PIEJ7-PIEJ0)
Yes
Vector base + $CC
$66
Port H
I bit
PIEH (PIEH7-PIEH0)
Yes
Vector base + $CA
$65
Modulus down counter underow
I bit
MCCTL(MCZI)
No
Yes
Vector base + $C8
$64
Pulse accumulator B overow
I bit
PBCTL(PBOVI)
No
Yes
Vector base + $C6
$63
CRG PLL lock
I bit
CRGINT(LOCKIE)
Refer to CRG
interrupt section
Vector base + $C4
$62
CRG self-clock mode
I bit
CRGINT (SCMIE)
Refer to CRG
interrupt section
Vector base + $C2
$61
SCI6
I bit
SCI6CR2
(TIE, TCIE, RIE, ILIE)
Yes
Vector base + $C0
$60
IIC0 bus
I bit
IBCR0 (IBIE)
No
Yes