Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
MC9S12XE-Family Reference Manual , Rev. 1.21
494
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
Figure 11-21. RESET Timing
11.5.1.1
Clock Monitor Reset
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
Clock monitor is enabled (CME = 1)
Loss of clock is detected
Self-Clock Mode is disabled (SCME = 0).
The reset event asynchronously forces the conguration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence
the S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the
clock quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the
S12XECRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running
in parallel to the reset generator, the S12XECRG may leave Self Clock Mode while still completing the
internal reset sequence.
11.5.1.2
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.
If the program fails to do this the S12XECRG will generate a reset.
11.5.1.3
Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
) (
)
(
)
SYSCLK
128+n cycles
64 cycles
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
ICRG drives RESET pin low
possibly
SYSCLK
not
running
possibly
RESET
driven low
externally
)
(
RESET
RESET pin
released