參數(shù)資料
型號: MC56F8006VLF
廠商: Freescale Semiconductor
文件頁數(shù): 39/106頁
文件大小: 0K
描述: DSC 16K FLASH 32MHZ 48-LQFP
標準包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據轉換器: A/D 24x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產品目錄頁面: 734 (CN2011-ZH PDF)
配用: MC56F8006DEMO-ND - DEMO BOARD FOR MC56F8006
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
General System Control Information
Freescale Semiconductor
38
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option
Power-saving clock gating for peripherals
Controls the enable/disable functions of large regulator standby mode with write protection capability
Permits selected peripherals to run in stop mode to generate stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls output of internal clock sources to CLKO pin
Four general-purpose software control registers are reset only at power-on
Peripherals stop mode clocking control
6.7
PWM, PDB, PGA, and ADC Connections
The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input.
The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB
pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of
PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006
Peripheral Reference Manual for additional information.
Figure 15. Synchronization of ADC, PDB
TriggerA
Pre-
TriggerA
TriggerB
+
PGA0 Controller
ANA15
ANA9
ANA7
ADHWT
ADCA
Trigger
SSEL[0]
SSEL[1]
ADCA
+
PGA1 Controller
ANB15 ANB8
ANB6
ADHWT
ADCB
Trigger
SSEL[0]
SSEL[1]
ADCB
Pre-
TriggerB
System
Clock
TMR0
TMR1
SW
CMP0
CMP1
CMP2
PWM
EXT
Trigger0
Trigger1
Trigger2
Trigger3
Trigger4
Trigger5
Trigger6
Trigger7
Programmable Delay Block (PDB)
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相關代理商/技術參數(shù)
參數(shù)描述
MC56F8006VLF 制造商:Freescale Semiconductor 功能描述:IC DSC 16BIT 16KB 32MHZ 3.6V LQFP-48
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