參數(shù)資料
型號: MC56F8006VLF
廠商: Freescale Semiconductor
文件頁數(shù): 52/106頁
文件大小: 0K
描述: DSC 16K FLASH 32MHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
配用: MC56F8006DEMO-ND - DEMO BOARD FOR MC56F8006
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
Overview
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
5
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
3.1.2
Operation Range
1.8 V to 3.6 V operation (power supplies and I/O)
From power-on-reset: approximately 1.9 V to 3.6 V
Ambient temperature operating range:
— –40 °C to 125 °C
3.1.3
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal flash
On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
EEPROM emulation capability using flash
3.1.4
Interrupt Controller
Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace
buffer
— Lowest-priority software interrupt: level LP
Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
The masking of interrupt priority level is managed by the 56800E core
One programmable fast interrupt that can be assigned to any interrupt source
Notification to system integration module (SIM) to restart clock out of wait and stop states
Ability to relocate interrupt vector table
3.1.5
Peripheral Highlights
One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
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