參數(shù)資料
型號: MC56F8013MFAE
廠商: Freescale Semiconductor
文件頁數(shù): 110/126頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
標準包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 32-LQFP
包裝: 托盤
56F8013/56F8011 Data Sheet, Rev. 12
84
Freescale Semiconductor
Figure 6-16 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8013/56F8011 offers security features intended to prevent unauthorized users from reading the
contents of the flash memory (FM) array. The 56F8013/56F8011’s flash security consists of several
hardware interlocks that prevent unauthorized users from gaining access to the flash array.
After flash security is set, an authorized user is still able to access on-chip memory if the user purposely
includes a subroutine to read and transfer the contents of internal memory via serial communication
peripherals, as this code would defeat the purpose of security.
7.1 Operation with Security Enabled
After the user has programmed the flash with his application code, the 56F8013/56F8011 can be secured
by programming a security word ($E70A) into program memory location $00 1FF7. This nonvolatile word
will keep the device secured through reset and through power-down of the device. Refer to the flash
RST
MSTR_OSC
CKGEN_RST
SYS_CLK_x2
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
PERIP_RST
CORE_RST
Switch on falling OSC_CLK
96 MSTR_OSC cycles
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension
Switch on falling SYS_CLK
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