參數(shù)資料
型號: MC56F8013VFAER2
廠商: Freescale Semiconductor
文件頁數(shù): 50/126頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-LQFP
包裝: 帶卷 (TR)
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
3
Rev. 8
In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
Rev. 9
In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
Rev. 10
Added the following note to the description of the TMS signal in Table 2-3:
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
Rev. 11
Removed “Preliminary” and made changes throughout the book, including changes in the
following sections:
Feature additions to Section 1.1.4
Deleted Section 1.4.1
Added diagram in Section 3.5.1
Added paragraph to Section 5.3
Deleted Section 5.5, “Operating Modes”
Added features to Section 6.2
Deleted note from Section 6.3.8.3
Clarifications to Section 6.3 register descriptions
Removed paragraph from Section 6.4
Rev. 12
Updated temperature information in Table 10-1 and Table 10-4.
Fixed miscellaneous errors.
Document Revision History (Continued)
Version History
Description of Change
Please see http://www.freescale.com for the most current data sheet revision.
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