參數(shù)資料
型號: MC56F8346VFVER2
廠商: Freescale Semiconductor
文件頁數(shù): 108/178頁
文件大小: 0K
描述: IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝: 500
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 帶卷 (TR)
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
Signal Pins
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
35
Preliminary
PWMA0
62
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA0 - 5 — These are six PWMA outputs.
PWMA1
64
PWMA2
65
PWMA3
67
PWMA4
68
PWMA5
70
ISA0
(GPIOC8)
113
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
ISA0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
Port C GPIO — These three GPIO pins can be individually
programmed as input or output pins.
In the 56F8346, these pins default to ISA functionality after reset.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOC_PUR register. For details, see Part 6.5.8.
ISA1
(GPIOC9)
114
ISA2
(GPIOC10)
115
FAULTA0
71
Schmitt
Input
Input,
pull-up
enabled
FAULTA0 - 2 — These three fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions originate
off-chip.
To deactivate the internal pull-up resistor, set the PWMA0 bit in the
SIM_PUDR register. For details, see Part 6.5.8.
FAULTA1
73
FAULTA2
74
PWMB0
34
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMB0 - 5 — Six PWMB output pins.
PWMB1
35
PWMB2
36
PWMB3
39
PWMB4
40
PWMB5
41
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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