參數(shù)資料
型號: MC56F8346VFVER2
廠商: Freescale Semiconductor
文件頁數(shù): 29/178頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝: 500
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 帶卷 (TR)
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8346 Technical Data, Rev. 15
124
Freescale Semiconductor
Preliminary
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
1
ISAL[23:22]
Write
RESET
11111
1
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
ISAL[21:6]
Write
RESET
11111
1
Instruction Portion
Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
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