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參數(shù)資料
| 型號(hào)： | MC56F8356 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 56F8356 16-bit Hybrid Controller |
| 中文描述： | 56F8356 16位混合控制器 |
| 文件頁數(shù)： | 147/160頁 |
| 文件大?。?/td> | 1380K |
| 代理商： | MC56F8356 |
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Equivalent Circuit for ADC Inputs
56F8356 Technical Data
Preliminary
147
significantly reduced (by as much as 28%) the collective variation (spread) of the absolute error of
the population. It also significantly reduced (by as much as 80%) the mean (average) of the
absolute error and thereby brought it significantly closer to the ideal value of zero. Although not
guaranteed, it is believed that calibration will produce results similar to those shown above for any
population of parts including those which represent processing and temperature extremes.
10.17 Equivalent Circuit for ADC Inputs
Figure 10-23
illustrates the ADC input circuit during sample and hold. S1 and S2 are always
open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input
of the sample and hold circuit moves to V
REFH
- V
REFH
/ 2, while the other charges to the analog
input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about
V
REFH
- V
REFH
/ 2. The switches switch on every cycle of the ADC clock (open one-half ADC
clock, closed one-half ADC clock). Note that there are additional capacitances associated with the
analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog
input voltage, V
REF
and the ADC clock frequency.
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is
only connected to it at sampling time; 1pf
Figure 10-23 Equivalent Circuit for A/D Loading
10.18 Power Consumption
This section provides additional detail which can be used to optimize power consumption for a
given application.
Power consumption is given by the following equation:
Total power =
A: internal [static component]
+ B: internal [state-dependent component]
+ C: internal [dynamic component]
+ D: external [dynamic component]
+ E: external [static]
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(V
REFH
- V
REFLO
) / 2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC56F8356MFV60 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC56F8356MFVE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8356VFV60 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8356VFVE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8357 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-BIT HYBRID CONTROLLERS |
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