參數(shù)資料
型號(hào): MC68331CPV20
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144
封裝: TQFP-144
文件頁(yè)數(shù): 62/254頁(yè)
文件大小: 1366K
代理商: MC68331CPV20
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MOTOROLA
QUEUED SERIAL MODULE
MC68331
6-28
USER’S MANUAL
6
TDR again overwrites the data. TDRE is set when the data in TDR is transferred to the
shifter. Before new data can be written to TDR, however, the processor must clear
TDRE by writing to SCSR. If new data is written to TDR without first clearing TDRE,
the data will not be transmitted.
The transmission complete (TC) flag in SCSR shows transmitter shifter state. When
TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is
not automatically cleared. The processor must clear it by first reading SCSR while TC
is set, then writing new data to TDR.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame
is transmitted as a preamble to the following data frame. If TC = 0, the current opera-
tion continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The send break (SBK) bit in SCCR1 is used to insert break frames in a transmission.
A nonzero integer number of break frames is transmitted while SBK is set. Break trans-
mission begins when SBK is set, and ends with the transmission in progress at the
time either SBK or TE are cleared. If SBK is set while a transmission is in progress,
that transmission finishes normally before the break begins. To assure the minimum
break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of
break transmission. After break transmission, at least one bit-time of logic level one
(mark idle) is transmitted to ensure that a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE
and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data and break
frames are transmitted. The TC flag is set, and the TXD pin reverts to control by PQS-
PAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing
data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output (DDRQS), then write a one
to PORTQS bit 7. When the transmitter releases control of the TXD pin, it reverts to
driving a logic one output.
To insert a delimiter between two messages, to place nonlistening receivers in wakeup
mode between transmissions, or to signal a retransmission by forcing an idle line, clear
and then set TE before data in the serial shifter has shifted out. The transmitter finishes
the transmission, then sends a preamble. After the preamble is transmitted, if TDRE
is set, the transmitter will mark idle. Otherwise, normal transmission of the next se-
quence will begin.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCR1. Service routines can load the last byte of data in a sequence into the TDR,
then terminate the transmission when a TDRE interrupt occurs.
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PDF描述
MC68331CFC25 32-BIT, MICROCONTROLLER, PQFP132
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MC68331CFC16 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68331CPV20B1 制造商:Rochester Electronics LLC 功能描述:32BIT MCU,GPT,SIM,QSM - Bulk
MC68331CPV25 制造商:Rochester Electronics LLC 功能描述:32BIT MCU,GPT,SIM,QSM - Bulk
MC68331LPV20 制造商:Motorola Inc 功能描述:
MC68331MEH16 功能描述:32位微控制器 - MCU 32B MCU GPT SIM QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
MC68331MFC16 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:User’s Manual