MOTOROLA
ELECTRICAL CHARACTERISTICS
MC68331
A-10
USER’S MANUAL
A
14
AS, CS Width Asserted
tSWA
80
—
ns
14A
DS, CS Width Asserted (Write)
tSWAW
36
—
ns
14B
AS, CS Width Asserted (Fast Write Cycle)
tSWDW
32
—
ns
15
AS, DS, CS Width Negated6
tSN
32
—
ns
16
Clock High to AS, DS, R/W High Impedance
tCHSZ
—47
ns
17
AS, DS, CS Negated to R/W Negated
tSNRN
10
—
ns
18
Clock High to R/W High
tCHRH
023
ns
20
Clock High to R/W Low
tCHRL
023
ns
21
R/W Asserted to AS, CS Asserted
tRAAA
10
—
ns
22
R/W Low to DS, CS Asserted (Write)
tRASA
54
—
ns
23
Clock High to Data Out Valid
tCHDO
—23
ns
24
Data Out Valid to Negating Edge of AS, CS
tDVASN
10
—
ns
25
DS, CS Negated to Data Out Invalid (Data Out Hold)
tSNDOI
10
—
ns
26
Data Out Valid to DS, CS Asserted (Write)
tDVSA
10
—
ns
27
Data In Valid to Clock Low (Data Setup)
tDICL
5—
ns
27A
Late BERR, HALT Asserted to Clock Low (Setup Time)
tBELCL
15
—
ns
28
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
tSNDN
060
ns
29
DS, CS Negated to Data In Invalid (Data In Hold)7
tSNDI
0—
ns
29A
DS, CS Negated to Data In High Impedance7, 8
tSHDI
—48
ns
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)7
tCLDI
10
—
ns
30A
CLKOUT Low to Data In High Impedance7
tCLDH
—72
ns
31
DSACK[1:0] Asserted to Data In Valid9
tDADI
—46
ns
33
Clock Low to BG Asserted/Negated
tCLBAN
—23
ns
35
BR Asserted to BG Asserted (RMC Not Asserted)10
tBRAGA
1—
tcyc
37
BGACK Asserted to BG Negated
tGAGN
12
tcyc
39
BG Width Negated
tGH
2—
tcyc
39A
BG Width Asserted
tGA
1—
tcyc
46
R/W Width Asserted (Write or Read)
tRWA
115
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
tRWAS
70
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
tAIST
5—
ns
47B
Asynchronous Input Hold Time
tAIHT
12
—
ns
48
DSACK[1:0] Asserted to BERR, HALT Asserted11
tDABA
—30
ns
53
Data Out Hold from Clock High
tDOCH
0—
ns
54
Clock High to Data Out High Impedance
tCHDH
—23
ns
55
R/W Asserted to Data Bus Impedance Change
tRADC
32
—
ns
56
RESET Pulse Width (Reset Instruction)
tHRPW
512
—
tcyc
57
BERR Negated to HALT Negated (Rerun)
tBNHN
0—
ns
70
Clock Low to Data Bus Driven (Show)
tSCLDD
023
ns
71
Data Setup Time to Clock Low (Show)
tSCLDS
10
—
ns
72
Data Hold from Clock Low (Show)
tSCLDH
10
—
ns
73
BKPT Input Setup Time
tBKST
10
—
ns
74
BKPT Input Hold Time
tBKHT
10
—
ns
75
Mode Select Setup Time
tMSS
20
—
tcyc
76
Mode Select Hold Time
tMSH
0—
ns
77
RESET Assertion Time12
tRSTA
4—
tcyc
78
RESET Rise Time13,14
tRSTR
—10
tcyc
Table A-6a 20.97 MHz AC Timing, (Continued)
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit